1. Field of the Invention
Generally, the present disclosure relates to the field of manufacturing of integrated circuits and semiconductor devices, and, more particularly, to a pre- or post-manufacturing monitoring process for gate cut masks, for example, within the context of SRAM design as well as manufacturing in Fully Depleted Silicon On Insulator (FDSOI) technology.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, application specific integrated circuits (ASICs) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. Miniaturization and increase of circuit densities represent ongoing demands.
Photolithography, also termed optical lithography or UV lithography, is a process used in microfabrication to pattern parts of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photomask to a light-sensitive chemical “photoresist,” or simply “resist,” on the substrate. A series of chemical treatments then either engraves the exposure pattern into, or enables deposition of a new material in the desired pattern upon, the material underneath the photoresist.
Within photolithography, and owing to the fact that an ever persisting aggressive downscaling is present, for example, in the context of sub-28-nm or even sub-22-nm Very Large Scale Integrated (VLSI) Circuits CMOS technologies, one of the most important parameters is the critical dimension (CD) of devices formed on wafers. The critical dimension is the minimum feature size on the various structures formed on a wafer. This corresponds to the dimensions of the smallest geometrical features, such as interconnect line, contacts, trenches, fins, gates, etc., which may be formed during semiconductor device/circuit manufacturing using a given technology. It is also common to write two times the half-pitch. The CD generally corresponds to the linewidth of the photoresist line printed on the wafer. It reflects whether the exposure and development are properly chosen to produce geometries of the correct size. As such, the CD is an important control means.
For an exposure process to pattern a device correctly, the critical dimensions (CDs) of all critical structures in the device must be patterned to achieve the design target dimensions. When a resist used in the exposure process is exposed by a projected image and thereafter baked and developed, the resist tends to undergo complex chemical and physical changes. The final resist patterns are typically characterized by their CDs, usually defined as the width of a resist feature at the resist-substrate interface. While the CD is usually intended to represent the smallest feature being patterned in the given device, in practice, the term CD is often used to describe the line width of any resist feature.
Since it is practically impossible to achieve every target CD with no errors, the device is designed with a certain tolerance for CD errors. The resulting pattern is considered to be acceptable if the CDs of all critical features are within these predefined tolerances. For the exposure process to be viable in a manufacturing environment, the full CD distribution must fall within the tolerance limits across a range of process conditions that represents the typical range of process variation expected to occur during the manufacturing process.
The range of process conditions over which the CD distribution will meet the specification limits is referred to as the “process window.” The term “nominal” may refer to the center of a process window and may be defined by the best focus and best exposure dose. At best focus, the CD and edge placement error may be equal to predetermined target values.
The process window conditions take into consideration various process variations. In lithography processing, process window conditions typically have variations in dose (relative to nominal dose), focus (relative to nominal focus) and mask bias offsets. A process may be considered to have a manufacturable process window if the CDs fall within the tolerance limits, e.g., ±10% of the nominal feature dimension, over a range of focus and exposure conditions which are expected to be maintainable in production, for example.
Conventional manufacture of semiconductors may include a preparation of a wafer, i.e., a substrate, application of structures or pre-structures on the substrate, followed by a preparation of a photoresist and/or a mask above the structures. After exposure, such as exposure to UV light, development and removing of the photoresist, a measurement of CD usually suffers from poor resolution due to the material properties of the photoresist. After an etching step, removing at least parts of the mask CD is often only monitorable as a tip-to-tip measurement. To achieve a systematic, structural learning process, it is often needed to omit certain specific structures from the preparation process in order to enable better visibility of CD structures.
Therefore, there is a need to improve the monitoring of CD structures after a mask opening step so as to improve the visibility and resolution of CD structures in order to ultimately facilitate shrink development.